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Altera_Forum
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8 years ago

Parallel Flash Loader For MAX II .

Hi Everyone, I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash. I have been able to generate the IP by following AN478 and AN386. I have i...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thank you for your reply Vikas.

I am using the Quartus II 17.1 Standard edition.

I have followed the steps told by you and in the AN386.

My question was, do I need to generate a test bench for the vhdl file which calls the IP.

Regards,