P-tile PCIe what if is rx_st_ready_i deasserted?

HI,

You can find the explanation of rx_st_ready_i signal in user guide doc (page 57)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf

Pls see my reply below.

1. If the application deasserts rx_st_ready_i, what does this mean for the endpoint behaviour regarding the TLPs that are inbound towards the FPGA? Will these TLPs be dropped in PCIe core?

• If rx_st_ready_i is deasserted by the Application Layer on <n> cycle , the Transaction Layer in the PCIe Hard IP continues to send traffic up to <n>+ readyLatency cycles after the deassertion of rx_st_ready_i. P tile ready latency is 27 clk cycles.
  • You can refer to further explanation and timing diagram in chapter 4.4.3. Avalon-ST RX Interface rx_st_ready Behavior (page 62)

1. is it even allowed to deassert rx_st_ready_i for a well-behaving PCIe endpoint ?

• The answer is YES but not recommended. Ideally to achieve the best performance, the Application Layer must include a receive buffer large enough to avoid the deassertion of rx_st_ready_i
  • This is just extra back pressure mechanism available for the application host to use if they need to

In short, when application layer deassert rx_st_ready_i, P-tile hard IP will gradually stop transferring TLP packet back to host and it will resume the packet transfer once rx_st_ready_i is asserted back

Thanks.

Regards,

dlim