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danield17's avatar
danield17
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1 year ago

Over 4GB PCIe BAR Size Issue

Hi, I created a design that utilizes the Arria 10 Hard IP and an EMIF. On my board, I have 8GB of DDR memory, and I wanted to connect one of the PCIe BARs to the EMIF so I could read from and write...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Daniel,


My apologies for the delayed response.


Please address the following questions for us to better understand the situation.


1. Could you please share the steps of your testing when using the BAR2?

2. Could you elaborate more on the failure situation where you were unable to read from or write to this BAR2? What are the outputs when you tried to read/write the BAR2?

3. From your description, my understanding is that when you checked the Enable burst capability for RXM BAR2 port, you observed that read/write to the BAR2 was good regardless of the BAR size 2/4GB. On the other hand, when this parameter is unchecked, it doesn't work properly. Is my understanding correct?

4. When I used the Address Span Extender to reduce the BAR size to 2GB, I was able to read and write. However, when I increased it to 4GB or above, it no longer worked.

Does this occur when the Enable burst capability for RXM BAR2 port is unchecked, and only on BAR2? Have you tried other BARs?


Thanks.

Best Regards,

Ven


  • danield17's avatar
    danield17
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Ven,

    1. I'm using my own application, which I'm confident is functioning correctly. Through it, I read from BAR2 at the EMIF offset.

    2. In the failure scenario, the values I read were all 0xFFs. Even after attempting to write to the same offset, I continued to read only 0xFFs.

    3. When the parameter was unchecked, I could only read/write successfully if the BAR size was set to 2GB.

    4. Read and write operations only worked when burst capability was enabled. I also tried using other BARs and encountered the same issue as with BAR2 when burst was disabled.

    Regards,
    Daniel

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 year ago

      Hi Daniel,

      The DMA master interface is also connected to the EMIF, and with DMA, both reads and writes work as expected. But with the BAR2 master, it didn’t work.
      >> Do you have any log or .stp showing failure vs passing scenario ?
      >> With that, we can better understand how the fail behave.

      I'm using my own application, which I'm confident is functioning correctly. Through it, I read from BAR2 at the EMIF offset.
      >> do you ever try out the design example that we provided https://www.intel.com/content/www/us/en/design-example/714464/intel-arria-10-fpga-an708-pcie-3-0-x8-avalon-memory-mapped-direct-memory-access-dma-with-external-memory-design-example.html

      >> If not, maybe you can try that and see if the same scenario happen (ONLY if you have time, else we can continue debug your design). BUT , trying that will help to narrow down where the fail coming from and help to accelerate our debug progress - I left the decision back to you.

      Read and write operations only worked when burst capability was enabled. I also tried using other BARs and encountered the same issue as with BAR2 when burst was disabled.
      >> is it compulsory for your design to disable the burst mode ?

      Additional information
      >> Based on my experience IF the Avalon bus implementation does not use the burst. When the memory controller receives a read transaction but the number of write data beats does not match what has been indicated by the busrtcount signal then I assume it will wait for more write data before processing the read.
      >> That could be the reason why you seeing those delay.

      Regards,
      Wincent_Altera