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danield17's avatar
danield17
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1 year ago

Over 4GB PCIe BAR Size Issue

Hi, I created a design that utilizes the Arria 10 Hard IP and an EMIF. On my board, I have 8GB of DDR memory, and I wanted to connect one of the PCIe BARs to the EMIF so I could read from and write...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Daniel,

I will look into your issue with the PCIe IP.

Could you please share the pcie.ip file used in your design? I would like to understand further the parameters and settings you have configured.

Thanks.
Best Regards,
Ven

  • danield17's avatar
    danield17
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Ven,

    Sorry for the delay in getting back to you.

    I’ve attached the PCIe IP file along with the Quartus project in case you’d like to take a look.
    As I mentioned earlier, everything worked fine when I was using the burst master.
    The issue only came up when I used the BAR2 master without bursting.
    The DMA master interface is also connected to the EMIF, and with DMA, both reads and writes work as expected. But with the BAR2 master, it didn’t work.

    Best Regards,

    Daniel