Over 4GB PCIe BAR Size Issue

Hi Adzim,

I’ve already created a design that uses DMA and the Address Span Extender, with my BAR set to 2GB, and everything worked fine.

I haven’t tried the EMIF example design, but I’ve confirmed that I can read and write to the DDR using both the DMA and the BAR master.

After investigating the issue, I found that read and write operations only work for me when the PCIe Hard IP is configured with burst enabled for the BAR2 master.

Is there a reason it only works with the burst master? Could it be something internal to the PCIe IP?

Did I miss something that would cause it to work only in burst mode?

Do you still want snapshots and the DDR datasheet? If so, how should I provide the snapshots—images?

Regards,

Daniel