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danield17's avatar
danield17
Icon for New Contributor rankNew Contributor
1 year ago

Over 4GB PCIe BAR Size Issue

Hi, I created a design that utilizes the Arria 10 Hard IP and an EMIF. On my board, I have 8GB of DDR memory, and I wanted to connect one of the PCIe BARs to the EMIF so I could read from and write...
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Pcie
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Daniel,


I'm Adzim from Altera. I will assist you in this case.


Have you verified that you are able to access 8GB DDR before? -maybe use difference design such as EMIF example design.


We need to make sure the EMIF IP setting is set correctly for the DDR that you used.

Can you provide the EMIF IP setting (can share the snapshot of the EMIF IP setting) and the DDR/memory datasheet?


Regards,

Adzim


  • danield17's avatar
    danield17
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Adzim,

    I’ve already created a design that uses DMA and the Address Span Extender, with my BAR set to 2GB, and everything worked fine.

    I haven’t tried the EMIF example design, but I’ve confirmed that I can read and write to the DDR using both the DMA and the BAR master.

    After investigating the issue, I found that read and write operations only work for me when the PCIe Hard IP is configured with burst enabled for the BAR2 master.

    Is there a reason it only works with the burst master? Could it be something internal to the PCIe IP?

    Did I miss something that would cause it to work only in burst mode?

    Do you still want snapshots and the DDR datasheet? If so, how should I provide the snapshots—images?

    Regards,

    Daniel

    • VenT_Altera's avatar
      VenT_Altera
      Icon for Frequent Contributor rankFrequent Contributor
      1 year ago

      See below message.