on-chip memory timing diagram

It sounds like you didn't yet understand the synchronous operation of the on-chip RAM. All control signals as well as input data and addresses are registered on the rising edge of the respective clock.

In so far the timing is defined very strictly, you have to keep the setup and hold times (as said, the Quartus timing analysis will check it in most cases) for these signals, a handshake signal won't serve a purpose. Basically you can write and read new data for each clock cycle.