On an ArriaV with a PCIe Gen2 x1, I would like a simple DMA engine and I noticed the IP for Avalon-MM DMA core requires a x4.

Question

Short of re-spin of the board, can I 1) use the x4 Avalon-MM DMA and only connect x1?  or 2) is there an example design that utilizes the DMA_Controller IP or similar with the PCIe IP?

boont_intel · Answer

Hi Sir, it is true that you need x4 lane for PCIE AVMM DMA. The x1 will not work because it unable to meet the bandwidth requirement that need from the DMA. conclusion is you might still see the LTSSM is work, but memory transfer will fail.

You may get the reference design from this AN:-

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an690.pdf

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On an ArriaV with a PCIe Gen2 x1, I would like a simple DMA engine and I noticed the IP for Avalon-MM DMA core requires a x4.

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