Forum Discussion

New Contributor

7 years ago

Not able to perform PCIe IP read and write to on-chip memory in Stratix V FPGA. The QSYS that I created should perform simple write into and read from on-chip memory via BAR2 of PCIe IP. It's reading all 0xFF and sometimes going for hang.

FPGA Name: Stratix V FPGA(Part name: 5sgxea7k2f40c2 ; Board Name: Bittware's S5-PHQ. Reference Design : Altera PCIe example design for connections and parameter settings A QSYS with "V Series A...

SengKok_L_Intel

Regular Contributor

7 years ago

I would suggest you to add a signaltap to capture the interface of BAR4 and on-chip memory (good case), and compare against with your custom logic (fail case). It should be able to help to understanding the problem further.

Regards -SK

Forum Discussion

Not able to perform PCIe IP read and write to on-chip memory in Stratix V FPGA. The QSYS that I created should perform simple write into and read from on-chip memory via BAR2 of PCIe IP. It's reading all 0xFF and sometimes going for hang.

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