Not able to perform PCIe IP read and write to on-chip memory in Stratix V FPGA. The QSYS that I created should perform simple write into and read from on-chip memory via BAR2 of PCIe IP. It's reading all 0xFF and sometimes going for hang.

I tried the reference setup given in the above link, it started working i.e., writing into on-chip memory via BAR4 of PCIe. But when I add my custom logic in to the QSYS, I'm facing the similar problem as I faced before(i.e., reading all 0xFF's from the slave interface of my custom logic and than system is going for restart )

custom logic details : Consists of slave interface of data width 32 bits, connected to BAR4 of PCIe. Than I tried to write into register via this slave interface using BAR4, and than I tried to read back from that register(via that slave interface) using BAR4, than I'm reading all 0xFF's and later system is going for restart