Forum Discussion
UTech
New Contributor
New ContributorNot able to perform PCIe IP read and write to on-chip memory in Stratix V FPGA. The QSYS that I created should perform simple write into and read from on-chip memory via BAR2 of PCIe IP. It's reading all 0xFF and sometimes going for hang.
FPGA Name: Stratix V FPGA(Part name: 5sgxea7k2f40c2 ; Board Name: Bittware's S5-PHQ. Reference Design : Altera PCIe example design for connections and parameter settings A QSYS with "V Series A...
SengKok_L_Intel
Regular Contributor
Regular ContributorIt seem like you are not using Altera Stratix V development kit.
For your information, here is the example design from AlteraWiki:
https://fpgawiki.intel.com/wiki/Reference_Design_-_Stratix_V_AVMM_DMA
You may ensure above design is working first, before enable the BAR2 for testing. To further debug this issue, you may need to capture the signaltap for BAR2 to identify the activity happened at the Avalon MM interface to Onchipmemory are expected for memory read or memory write command.
Regards -SK
