Forum Discussion
Honored ContributorNIOS TSE initialize
Dear All,
I am new in NIOSII and TSE. I use the Altera developemnt DK-DEV-4CGX150N for project development. I use the Qsys to build up my system and want to write some code to make the development board to TX some data to my PC. I use a sniffer program to capture the data TX to my PC. In my current situation, I cannot receive any data at the PC. My program flow is as below: 1. Hardware reset the PHY. 2. Initialize the phy (mdio address, change to RGMII mode...) 3. Software reset the TSE 4. Setup those FIFO threshold of the TSE 5. Disable both shift 16 for TX and RX 6. Set the TSE CMD config to enable the TSE 7. Set the MAC address of TSE 8. Set up SGDMA device and descriptor 9. Send data to my PC. I reference to the examplet program in following thread to build my program. But still not work. "tse mac and marvell 88e1111 " I attached herewith is a few files of my design for your refrence. I believe that the issue is due to the initialize process of my TSE and phy. Would any one provide some advice on it. Thanks for your kind help in advance. Best Regards, Albert Siu23 Replies
Altera_ForumI understand that those reference design can help me to understand on how to control the TSE. But I cannot download it to my development board after I compile it on the NIOS SBT (I can sure I already program the FPGA with proper sof file).
Also I cannot find those code for initialize the TSE within the simple socket server example. The example use UCOS and nichestack. And it call some UCOS function to initialize the system but I cannot view the code in detail. Another major concern is both of them is not free of charge, so I intend not to use both of them.- Altera_Forum
Try to run the example first. If it runs fine, then You can test Your own design.
- Altera_Forum
I agree with Socrates. Begin with a configuration that works and go from there. Both the TSE and the PHY must be initialized properly and it's better to be sure that your hardware configuration and FPGA image work properly before looking into the software.
What do you mean by "I cannot download it to my development board"? - Altera_Forum
I try to use debug as -> NIOS II hardware to download the reference design to my development board for testing. Sometime later NIOS SBT pop up a window and indicate that I cannot download the elf into my development board.
I can downlaod some simple self design program to control LED on the board. - Altera_Forum
What is the *exact* error message?
- Altera_Forum
SBT report "Downloading ELF process fail". As per the screen capture.
The same error message appear even I reboot my PC. - Altera_Forum
We need to see what's going on in the console when you try to upload the software in the FPGA, it will tell more where the problem is coming from.
Are you sure you uploaded the correct configuration in the FPGA first? - Altera_Forum
I can sure I download the correct FPGA configuration into my development board. Is there any method for me to counter check against this?
- Altera_Forum
If You are not able to paste console output to the pastebin and paste link here, how can You be sure You are able to download the design at all?!
- Altera_Forum
Attached is the screen capture when I choice debug as in NIOS SBT. I do not capture the screen of Quartus II programmer. As it report 100% download success in that process. Please let me knwon if more information is required for fixing my issue. Thx.
