New IP development

Hello,

Appreciate the response :). I will explain my problem description.

I was planning to make the NIOS II processor do some bigdigit instructions so that it can support the encryption schemes (like an RSA) from an application code.

An RSA needs to handle some bigdigits operation like arbitrary precision integer multiplication, modulus operation etc and there are FPGA hardware

modules which implements that. However there is no work done in the area where one can execute the RSA from a NIOS II application code (from the Eclipse IDE).

So I thought it will be nice if we can develop some instructions the NIOS II processor can call and execute for doing some bigdigits math. I tried to look into more custom instructions but those were very much constrained. Then I came across the IP development concept, however the base issue is the same as you pointed out. It is not possible to give a data type which is more than 32 bit wide from NIOS II to any component since the processor itself is 32 bits wide (the data path). One approach is to give 32 * 32 data bits and have logic inside my custom IP to handle those. However waiting for 32 clock cycles for a 1024 bit data can affect the throughput of the custom IP instruction that I am planning to implement.

Will discuss this matter with my professor and I can update you as well. Hope my problem description is clear.

Thank You,

Akhil