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dinkersemwal's avatar
dinkersemwal
Icon for New Contributor rankNew Contributor
5 years ago
Solved

NCO IP output is shifting wrt output valid on aria10 eval board

Hi All, I am using intel NCO IP as DDS to generate a LO for the mixer. when i am testing my module on board(aria10 eval), i observe that output sample is shifting by one clock (back and forth wit...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    4 years ago

    Hi,

    This might be related to the reset, you probably need to hold the reset for a few clock cycles while the clken is asserted.


    Regards -SK


SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

In the user guide, it states the reset is asyn, however, based on the waveform, the reset is de-asserted during the clk_en is asserted.