Forum Discussion
Rahul_S_Intel1
Frequent Contributor
6 years agoHi,
I am requesting to go through the below document, and in that if you are
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_nco.pdf
The RESET_N signals are asynchronous signal.
- RDobk6 years ago
New Contributor
Hi, I am familiar with this document. Unfortunately, it does not answer my questions: 1. Is there any minimal width for RESET_N in terms of clock cycles? 2. Should assertion of CLKEN always precede the RESET_N de-assertion (reset release)? if so, by how many clock cycles? 3. Are there any additional requirements for timing for RESET_N (e.g. should it de-assertion be synchronized to the clock of the NCO)? In the lab, I observe that Enabling the NCO after reset de-assertion has a non-deterministic effect on the NCO output – after such reset the NCO initial delay (reset/Clken -> DV_OUT) is non deterministic. Thus the questions is, what is the correct order/way to reset and then leave the reset for the NCO. Best regards, --Reuven.