NCO and FIR COmpiler Megafunction performance

For understanding the effect of no. of bits of output, i wrote a simple code :

module testing (in1, in2, out,out1, out2);
input  in1;
input  in2;
output  out;
output  out1;
output  out2;
assign out = in1 + in2;
assign out1 = in1 + in2;
assign out2 = in1 + in2;
endmodule 

this design i simulated with unsigned decimals. in1 and in2 = 1 to 36;

the various outputs are as shown in attachment.

http://www.alteraforum.com/forum/attachment.php?attachmentid=6206&stc=1&d=1345964169

The same design i simulated for signed decimal input. and result is :

http://www.alteraforum.com/forum/attachment.php?attachmentid=6207&stc=1&d=1345964401

CLEARLY :

I believe, in verilog, if we assign a higher no. of bits to output, the result doesnt vary or affected by the nature of input viz. signed/unsigned etc.

what do u think ??