NCO and FIR COmpiler Megafunction performance

In VHDL, the result length of an add operation is just the same, the length of the largest summand. There's however an important difference that helps you to avoid the observed overflow problem, VHDL doesn't allow to assign the 18 bit sum to a 19 bit variable:

Error (10344): VHDL expression error at unsigned_adder.vhd(27): expression has 18 elements, but must have 19 elements

In VHDL, an automatic length extension of add result would be unwanted, because an overflow within the same result width is often required, e.g. for counters.

In less strictly typed Verilog, an automatic extension would be an option, but obviously the language designers decided differently.