NCO and FIR COmpiler Megafunction performance

Thanks FvM for the note. However in that case it is not really misunderstanding of verilog(or vhdl) by the designer but rather misunderstanding of designer by verilog or vhdl.

common sense tells me that if result is 19 bits and operands are 18 bits then why on earth would the result depend on input width and not output width.

Normally in vhdl adder inference - a far as I remember - it does not let input width be less than output forcing in effect avoidance of this scenario,

So in short, it is a ludicrous mistake in the standards to be that misleading.