Honored Contributor
Honored ContributorHi,
I found a hack as a workaround since I had exactly the same problem with the Terasic DE4 board (Stratix IV GX 230), channel 1 works but channel 2 had that same critical warning. The DE4 board has several dedicated clock pins distributed among different banks, so DRAM channel 1 which has pins on the bottom edge of the board should use a bottom PLL so it needs a clock pin in one of the bottom banks. It turns out that there is only 1 dedicated PLL input pin in the top banks where DRAM channel 2 has its pins and it was not the one that the templates from Terasic suggested. This is where some hacking comes in: Take a look at the pin planner for your device, find all the clock pins that are in the same I/O banks as where DRAM channel 2 has its pins. I'm using Quartus 9.1 and clock pins have a round icon that inside has what looks like a rising edge waveform (some also have a falling edge). Using a self-made blinking LED test (takes like 15 minutes to put together), I found out which clock pins are actually connected to the board's oscillators and which are dedicated PLL clock input pins (after compiling check the warnings in Quartus so see whether each clock pin got a node promotion to a global clock, or some similar warning). Currently preliminary experiments are working, both channels operate at 400 MHz but channel 1 uses a 50 MHz input (OSC_50_BANK3, PIN_AV22 in my case) and channel 2 uses a 100 MHz input (GCLKIN, PIN_A21 in my case), so I have 2 separate mega-wizard generations each instantiated once. Good luck and have fun, Jason
