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Altera_Forum
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15 years ago

Multiple Memory Interfaces with MegaWizard Plug-in Manager Flow

Hello, I am trying to implement two memory controllers (dual channel) in Stratix IV device. FPGA have enough resources for two controllers so I don't need to share the DLL or PLLs. I have dupli...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello,

I have narrowed down the problem. My FPGA (StratixIV GX 530) has two DRAM channels. I am using DDR2 High Performance Controller and I have DDR2-800 SODIMMs. When I use the channel A for my I/O everything works fine. When I switch the I/O pins to the channel B, I got the errors above. Everything is same except the pin assignments for my memory controller.

For channel B design I am sure that I have the correct pin assignments. Since it complains about the clock input to PLL I tried couple other clock inputs with 1.8V I/O standard. Still same issue. Any ideas?