Multiple DSP Builder designs with conflicting VHDL

We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA.

The problem is that these various DSP Builder designs use identical filenames within their project for similar functions. For example, if 2 designs use a 1-cycle delay block, then that delay block is generated in both DSP Builder designs, and when we pull in each project, 2 of these .vhd files are imported.

Naturally, when Quartus II compiles 2 of these files, both with the same filename and entity name, an error occurs (Quartus doesn't know which entity to use). It has gotten to the point that there are just too many duplicate files (hundreds) to hand edit and/or delete. Has anybody else encountered this situation, and if so, how did you solve it?

Thanks,