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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multiple DSP Builder designs with conflicting VHDL

We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA. The problem is that these various DSP Builder designs ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

And it works - ok, source files generated from DSP-Builder that have the same filename/entity are being overwritten. But they have identical content (at least in my case) - so all design information exported from Simulink/DSP-Builder is still available top level design (see thread# 154841).

It's also possible to keep separate HDL folders for each module and just remove duplicate entries from the other .qip-file(s).

Thanks souvir for this great tip. :)