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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multiple DSP Builder designs with conflicting VHDL

We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA. The problem is that these various DSP Builder designs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I solved the problem by generating all the VHDL files into one directory, so that same file will be coverd. And all the qip files point to unique file without conflict.

When I have free time, I will try qxp solution.

Thank you~