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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multiple DSP Builder designs with conflicting VHDL

We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA. The problem is that these various DSP Builder designs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

another work around is creating a QXP for each of the DSP Builder projects and integrating them into a single top level project. dabuk's solution of using the mdl instead sounds good too.