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Altera_Forum
Honored Contributor
Honored ContributorMultiple DSP Builder designs with conflicting VHDL
We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA. The problem is that these various DSP Builder designs ...
Altera_ForumHonored Contributor
Honored ContributorAre you including the mdl file directly into your top-level Quartus II project or are you including the HDL output of DSP Builder?
