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Altera_Forum
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13 years ago

Multi-Rate Designs

Hi, I'm having a problem driving different blocks of my design with different clock rates. Suppose I want the following system: Input Signal (50 MSPS) --> CIC Filter (decimate by 25) --> F...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The compare conditions in post# 1 aren't exactly clear to me. Do you run the same filter h(n) with different sample rates?

In a realistic testbench, the filter should be calculated for 2 MSPS input rate, sink_valid supplied with a 2 MHz clock enable and the test signal clocked at the same rate.