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Altera_Forum
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13 years ago

Multi-Rate Designs

Hi, I'm having a problem driving different blocks of my design with different clock rates. Suppose I want the following system: Input Signal (50 MSPS) --> CIC Filter (decimate by 25) --> F...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the response. I was not aware that the sink_valid input controls the FIR clock rate.

In the example with the impulse response, how would I tied the sink_valid signal to let the FIR know the input pulse is coming at 2 MSPS? Since the data is valid at the start of the pulse. There's no difference between that and the pulse at 50MSPS.

Thanks!