Multi-Rate Designs

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I cannot access the clk input to the FIR filter and force it to operate at a slower clock rate. The FIR seems to tied to the base clock and outputs at the fast rate.

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Why not reading the FIR compiler handbook? The FIR filter has sink_valid to command the input data rate. Simply wire it to CIC dout_valid.

Operating the FIR filter with multiple clock cycles per sample offers the option to save resources by selecting a serial or multibit serial topolgy.