Forum Discussion
NGord
Occasional Contributor
Occasional ContributorMSGDMA Read and Write Masters
Hi, The MSGDMA is deliberately designed to be modular. As such , if I wanted to utilise the Read and Write Master IP without the Dispatcher, there is no published specification for the Command and ...
Jeet14
Frequent Contributor
Frequent ContributorHi,
Please refer the example design for MSGDMA for Arria 10. This is having NIOS II, MSGMDA.
https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335
You can try porting above reference design to MAX 10.
Regards
Tiwari
