mSGDMA & WinDriver Wizard Code

I am working on implementing a Windows driver for a PCIe (gen1x4) on a Cyclone V GX development board using Jungo's WinDriver. My current Qsys project consists of a Altera's Avalon MM PCIe hard IP, XCVR Rconfig controller, On-Chip RAM, DDR3 interface and the mSGDMA (configured for MM-MM transactions) from Alterawiki. I am using Jungo WinDriver for the driver development. I used Jungo's code generation wizard with the Altera Qsys customization option enabled to generate the initial driver code. I have been trying to figure out the test application and perform simple memory transfers with the mSGDMA with little success. I am going through the source code and am trying to understand what is exactly going on. I was hoping that someone could explain the following snippet of code (from the DmaDevicePrepare function) to me and what is being accomplished there:

--- Quote Start ---

/* Try to check the address translation path through */

/* (0x1000 is the offset for the translation register) */

WDC_WriteAddr32(hDev, AD_PCI_BAR1, 0x1000, 0xFFFFFFFC);

/* Read the path through mask */

u32A2PMask = PCIE_QSYS_ReadReg32(hDev, AD_PCI_BAR1, 0x1000);

/* Program the address translation table */

/* The PCIe core limits the data size to 1 MByte, so it only needs a 20-bit

* address. */

/* Set the lower 32 bits of the DMA address */

WDC_WriteAddr32(hDev, AD_PCI_BAR1, 0x1000,

(DWORD)pDma->pDma->Page[0].pPhysicalAddr & u32A2PMask);

/* Set the upper 32 bits of the DMA address */

WDC_WriteAddr32(hDev, AD_PCI_BAR1, 0x1004, 0x0); /* Currently limited at

* hard IP */

--- Quote End ---

Where does this 0x1000 offset for the translation register come from? purpose of writing 0xFFFFFFFC to 0x1000?

I see the comments there, but want to understand the necessity of this. I thought that configuring a transfer would be as simple as writing to the dispatcher Read Address, Write Address & Length registers and setting the 'go' bit... Any explanation/insight/tips would be appreciated.