Modify Ariia V ALTLVDS_TX data rate during work

Are you trying to send data out at 1620 Mbps and 2700 Mbps, while inside the FPGA you have 10 bit words of 162Mbps or 270 Mbps? If so, LVDS doesn't run that fast and you need a higher speed protocol(which has overhead).

Or are you sending out data at 162Mbps or 270 Mbps? If that's the case, you probably don't even need altlvds and can build it out of logic.

(A third option is that your sending data out a 324Mbps or 540Mbps, as people often send data at double-data rate)

I don't have a sense of what you're doing. For the idea of sending a different reference clock to the altlvds block, probably not. Note that altlvds in Arria V has a PLL in it. By default it's instantiated inside(although you can change this so the PLL is external and you have to manually create it and hook it up). The PLL probably can't take an input frequency range that is that high, although I'm not sure.