Model-Sim tries to compile header files not included in my project and fails. Model-Sim also fails to instantiate FIFOs and potentially other IPs because it looks it the work_rtl library instead of the altera_mf library

I am trying to simulate my verilog modules in modelsim. When I try to include .v files as headers in my modules, modelsim still tries to compile them and complains that global variables are not allowed. I tried to circumvent this by including an .inc file instead(which seems to work?) and got past the compilation phase. Now when I try to simulate my top level module, I get the following error:

# ** Error: (vsim-3033) C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/output_fifo.v(74): Instantiation of 'dcfifo_mixed_widths' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /test_wrapper/inst/generate_structure[3]/output_fifo_inst File: C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/output_fifo.v

# Searched libraries:

# C:/Users/abdelfadel/Desktop/xillybus_beta_core_pipelined/verilog/simulation/modelsim/rtl_work

I am starting modelsim from Quartus by clicking on tools ->run simulation tool -> RTL simulation