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Wojtek_Poland's avatar
Wojtek_Poland
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4 years ago
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Model sim error - fPLL

Hi! After reading UG-20093 | 2019.12.30, i try to simulate fPLL (fractional PLL - Transceiver mode - 80MHz refclk, 570MHz output freq.) component. I got this error after including libraries and ...
  • Nurina's avatar
    4 years ago

    Hi,


    Since you are using Quartus Prime Pro edition, you will need to edit your .do file before you simulate your project. From your .do file you are missing a lot of commands:

    1. Compile all design and testbench files in your project. "vlog -vlog01compat -work work ../<design and testbench files>"
    2. This is to set the top-level simulation or testbench module/entity name. "set TOP_LEVEL_NAME <simulation top>"
    3. Call command to elaborate your design and testbench. "elab"
    4. To run the simulation. "run -a"


    You can refer to section 1.4 of this document to understand better: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf#page=6


    You also need to save your file as wojtek.do instead of wojtek.tcl.


    Best regards,

    Nurina