min max frequency requirement of altera IP components

The table JacoL suggested should be considered only a reference for performance, I'd say an asyntotic upper limit.

There are a lot of factors affecting the 'real' fmax you can attain.

Mainly:

- how much fpga resources are used

- how much resources are available for routing

- how much you are smart in placing timing constraints

For example, I've been told (and I've quite verified it) that on a Cyclone III device you can't expect to safely use Nios/f core at a frequency above 100-120 MHz, unless your fpga is almost empty and you thoroughly check the timings after every recompilation.

Regarding the lower frequency limits I don't know. I think this depends from pll minimum operating frequency.