Forum Discussion
Hi,
Thanks for reaching again.
- Do you try to run the example design without modification ? is it behave the same ?
- What kind of payload size you are using to do the test
- Did you develop your own driver or you are using our example design driver ?
- Did you capture the below signals to check if the data is mismatch or not ?
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_valid_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_data_o[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_ready_i
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_hdr_o[255:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_rx_st_sop_o[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_data_i[511:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_eop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_sop_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_ready_o
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_valid_i[1:0]
pcie_ed_tb.pcie_ed_inst.dut.dut.ast.p0_tx_st_hdr_i[255:0]
Looking forward to hear back from you.
Regards,
Wincent_Intel
Hi @Wincent_Altera , thanks for the reply,
we used the example design originally without modification and it was working, with both example driver and our driver.
Then we removed the packet generator/checker from the example to create our own design which also worked with both our driver and example design driver.
Then we tried to modify the MCDMA/PCIE core to 256 channels from 64, and this is where we start having problems. We used payloads of 8K for the 64 channel case, and 2K for the 256 channel case.
Why does the example design only use 64 channels? Why not 256 or the max 2K?
We are now in the process of trying the example design customized for 256 channels. We will try to get reports from the example driver to you.
We do monitor those signals in our design with signaltap but do not yet have a capture when it fails, but we'll keep trying.
regards,
Greg