maximizing read bandwidth of HP DDR2 memory controller

As long as you have only one slave port to the memory controller, you can not optimise (hide) the cycles for opening a new bank for read operations. If your reads are random spread, you have to live with the lower performance.

I have did some tests with the microtronics controller some time before ( in a single data rate configutation), and the result was rather dissapointing due to clock-domain synchronisations. In some cases it is better to have a slower clock to the memory and no clock domain synchronisation, instead of a high spead memory access, with big synchronisation penalty.

Stefaan