maximizing read bandwidth of HP DDR2 memory controller

thanks FvM. That's right, I don't think there's any perf questions when reading 1 continuous block of memory. The question is about efficiently managing multiple concurrent block reads the the HP controller (to still get ~max ddr2 bandwidth with minimal buffering and minimal worst-case latency).

I can hope that the Microtronix controller could end up doing better (if I redesign to use its multiple ports most efficiently), but this optimization requirement is specific enough that I'd believe I could make a more efficient solution with lower level control.

My coworker heard about an (Altera?) class for designing your own memory (ddr2?) controller. Perhaps I'll look into that for the long term solution.