Hi, I have generated the test bench, and it partially runs. For example in the simulation if I request a read I do get a response from the ufm, but the output data is always XXX. I know it is partially working because the waitrequest signal is toggled as expected. And when the data is output the readready signal is asserted on time. My problem is that no data can be written to the ufm and any time a try to read from it (in simulation) i get XXX in the output.
This is no matter if I tried to initialize the simulated memory with my own file or used the default setting in intel ip core.
would be glad for any help I can get,
Thanks
Ariel.