Max10 Soft LVDS bit slip shouldn't be needed for odd serialization factors. How to shift bits with external pll mode using nothing but compile time phase adjustments?

I have connected with an FAE under MNDA and am sharing files with them. At this time I believe some of my issues to be related to the lack of logic lock regions around the IP modules due to use of the Lite Edition. The modules are spread all over the FPGA fabric by the fitter rather than including some reasonable timing constraints applied by the megafunction wizard when the IP is generated. With the addition of some partially invalid routing path delay constraints that break the reported Fmax, the LVDS Tx core is more spatially constriained by the fitter and my code now functions on hardware. I do not have any explanation for the different bit-slip between the two cores. Since the data path is video data I have even tested routing half of the input data to my Tx port direct with routing and a subsequent frame grabber is able to capture the incoming feed reasonably well, that is to say, the input video streams are in fact properly timed.