Forum Discussion

WKett's avatar
WKett
Icon for New Contributor rankNew Contributor
6 years ago

Max10 Soft LVDS bit slip shouldn't be needed for odd serialization factors. How to shift bits with external pll mode using nothing but compile time phase adjustments?

Serialized bit phase alignment is deterministic for odd LVDS serialization factors as used by Channel Link interfaces.. In gate level simulation using Modelsim, I get properly phase aligned bits out...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Thank you for your suggestion and appreciate your input. Defintely i will provide your feedback to the internal team.

Coming back to the soft LVDs IP core buggy comment : " In my two identical Max10 receivers, I have to set bitslip to 6 in one of them and 5 in the other on hardware despite simulation of the .vo EDA netlist indicating that bit slip should be set to 5 on both" Can you kindly share the files so i can check and if it is a bug i will definetely raise the concern and fix it.

Actually my thought is it maybe issue with the model not the ip core but lets see . you can send to my email .

Thank you ,

Regards,

Sree