Max10 Soft LVDS bit slip shouldn't be needed for odd serialization factors. How to shift bits with external pll mode using nothing but compile time phase adjustments?

Hello there ,

Here is my comprehension of your first paragraph ,

Data from the LVDS port to the LVDS RX with respect to the clock is not aligned(skew).So you done the simulation by creating the training pattern know how many bits to slip to see right word.

and training pattern is not possible in your system. Hence your question is how to do this ; correct ?

Let me explain you training pattern has to be come from the external world ; from the simulation you can adjust the clock which is not actually referring the problem you might facing.

can you make sure it is clock or channel to channel skew ?

Also you were saying if serialization factor is odd so there is no need for training pattern ? Really ? i dont think so , Bit slip feature required because of the data skew or channel to channel Skew.

hence you are slipping the bit for a clock or more and see you are getting the right data.

Example , you expect to get the data 5A , but you get A5 because of the channel - channel Skew. By enabling the bit-slip and training pattern you can see how many clock you have to slip to get the

right data.

Thank you ,

Regards,

Sree