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SOtsr's avatar
SOtsr
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7 years ago

Max10 on chip flash ip core issue

I try to write data to the internal flash, noticed that somehow the waitrequest signal is asserted for one clock cycle only. The clock is 25mhz. I noticed it through the signaltap.. ​ Any idea?​
SOtsr's avatar
SOtsr
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7 years ago

so i checked the issue and noticed that in signal tap if i check the ports of the onchip flash (whithin the qsys) directly, i see that the waitrequest asserts for approximately 1.5 usec.

changed the avalon bridge parameter to disable all the pipeline features. and now i see differeent behave of the waitrequest.

but still, isnt it too short time?

another thing i noticed is that if i sample the readdata port of the csr interface of the onchip flash, i can see in live the status of the flash. ive seen that many times the write fail flag of the status register is asserted.

any idea why?