Max10 Eval Kit User Flash Memory IP

Hey everyone, I've been trying

As a sidenote - I have read the MAX10 User Flash Memory guide in its entirety no fewer than 3 times, however, I have almost zero experience in verilog.

I'm trying to use the push buttons on my development kit to "one step" my way through the Altera Flash IP core, and reading out significant signals to the leds on board as a troubleshooting tool. My problem is currently, I try to write to the CSR control register, then read back the CSR control register to verify my changes went though - they never do. Any guidance as to where to go from here (or if I'm completely off course..) would be greatly appreciated. Here's my verilog code. Thanks!

module FlashMemory(

clock,

pbs,

led

);

input clock;

input [3:0]pbs;

output [4:0]led;

/////////////////////////

reg[31:0] writedata = 32'h00000000;

reg[31:0] readdata;

reg[15:0] dataaddress = 16'h0004;

reg[31:0] readdatacopy = 32'hFFFFFFFF;

reg datawrite = 1'b0;

reg dataread = 1'b0;

reg burstcount = 1;

reg busy;

/////////////////////////

reg[31:0] csrwritedata = 32'h001FFFFF;

reg[31:0] csrreaddata;

reg[15:0] csraddress = 16'h0001;

reg csrhighbit = 1'b1;

reg csrwrite = 1'b0;

reg csrread= 1'b0;

/////////////////////////

reg reset;

wire pllclock;

wire locked;

wire readdataok;

reg [4:0]led = 5'b11111;

reg writebutton;

reg readbutton;

reg csrwritebutton;

reg csrreadbutton;

reg csrwriteprotection;

reg dummy = 1'b0;

reg [31:0] writetimer = 0;

always @(posedge pllclock) begin

if(dummy)begin

reset <= 1'b0;

end

/////////////////////////

else begin

reset <= 1'b1;

csrwritebutton <= pbs[0];

csrwriteprotection <= pbs[1];

csrreadbutton <= pbs[2];

if(!pbs[0] && csrwritebutton)begin

csrwritedata <= 32'h001FFFFF;

csrwrite <= 1'b1;

end else if(!pbs[1] && csrwriteprotection) begin

csrwritedata <= 32'hFFFFFFFF;

csrwrite <= 1'b1;

end else begin

csrwrite <= 1'b0;

end

if(!pbs[2] && csrreadbutton) begin

csrread <= 1'b1;

end else begin

csrread <= 1'b0;

end

if(!csrreaddata[31]) begin

csrhighbit <= csrreaddata[31];

end

if (csrread) begin

led[0] <= 1'b0;

end

if (csrhighbit)begin

led[4] <= 1'b1;

end

if (!csrhighbit)begin

led[4] <= 1'b0;

end

end

end

FlashIP FlashIP_inst (

.clock (pllclock), // clk.clk

.reset_n (reset), // nreset.reset_n

.avmm_data_addr (dataaddress), // data.address

.avmm_data_read (dataread), // .read

.avmm_data_writedata (writedata), // .writedata

.avmm_data_write (datawrite), // .write

.avmm_data_readdata (readdata), // .readdata

.avmm_data_waitrequest (busy), // .waitrequest

.avmm_data_readdatavalid (readdataok), // .readdatavalid

.avmm_data_burstcount (burstcount), // .burstcount

.avmm_csr_addr (csraddress), // csr.address

.avmm_csr_read (csrread), // .read

.avmm_csr_writedata (csrwritedata), // .writedata

.avmm_csr_write (csrwrite), // .write

.avmm_csr_readdata (csrreaddata) // .readdata

&nbsp;);

FlashPLL FlashPLL_inst (

.inclk0 ( clock ),

.c0 ( pllclock ),

.locked ( locked)

&nbsp;);

endmodule