DR123New Contributor6 years agoMAX 10 EMIF DDR3 velocity transfer issue Hi, I'm working on a DECA development board and I'm trying to transfer data from a FIFO to the on-board DDR3 through a Scatter Gather DMA and an EMIF controller for the DDR. The data are correctly t...Show More
Recent DiscussionsAgilex 7 slew rate reconfigurationSolvedAgilex-7 AXI MCDMA for PCIe hangConstraints not being picked for DCFIFOCan't generate F-Tile Ethernet Hard IP Design ExampleMAX10 TSE reference design