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DR123's avatar
DR123
Icon for New Contributor rankNew Contributor
6 years ago

MAX 10 EMIF DDR3 velocity transfer issue

Hi, I'm working on a DECA development board and I'm trying to transfer data from a FIFO to the on-board DDR3 through a Scatter Gather DMA and an EMIF controller for the DDR. The data are correctly t...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi the ready signal that you mentioned here is avl_ready from the DDR3 controller? If this case, seem like the transfer issue is not come from the controller.

I don't think the waitrequest signal is come from the DDR3 controller, the status signal come from DDR3 is avl_ready but not waitrequest. Please check the waitrequest is come from which component and the issue suppose come from it. Maybe the DMA or Qsys interconnect?