Forum Discussion
@jozephka99 That's also my understanding, except that the manual says onchip_flash_csr_writedata(22 downto 20) "101" for image 0 (sector 5) and "100" and "011" for image 1 (sector 4 and sector 3).
Anyway, I also tried this, no luck. Both for the writedata(22 downto 20) addresses mentioned by Jozephka99 and those mentioned in the manual.
I've added my latest project as a zip file. In this latest test, I even just exported the csr interface and manually connected my signals to it.
I hope to find time this week to setup the signal tap so I can see what goes on in the actual FPGA and why this is failing. (or at least gives the impression of failing)
Already many thanks for the different people replying to this topic and helping me figuring this out!
"timeout" component file missing. So I cannot compile that project. Can you provide it?