Occasional Contributor
ContributorLet do a CFM erase operation from beginning:
1. In one cycle, set:
csr_write <= '1'
csr_address <= '1'
csr_writedata(31 downto 23) <= "111100000" --Write protection off for all sectors (max: 2 ufm, 3 ufm. Your device may not have all of this but it don't broke the program.)
onchip_flash_csr_writedata(22 downto 20) <= sector_erase_addr; -- "100" for image 0, "010" and "011" for image 1 (you have to clear one by one for each sector in image 1)
onchip_flash_csr_writedata(19 downto 0) <= "11111111111111111111"; -- rest default
2. In the next cycle, set:
csr_write <= '0'
And wait 350 ms. (Max sector erase time)
3. If you want to erase image 1, go back to first step and set other sector id.
4. Here, your sector must be cleared. You can check it from erase succesfull flag. If you don't have any configuration in the other image you cannot run the fpga if you power-cycle as you said. You don't have to deal with data interface just for clearing. And if you want to check it is really cleared the sector you should read the sector and if it is all FF's then erasing is succesfull.
Occasional Contributor@jozephka99 That's also my understanding, except that the manual says onchip_flash_csr_writedata(22 downto 20) "101" for image 0 (sector 5) and "100" and "011" for image 1 (sector 4 and sector 3).
Anyway, I also tried this, no luck. Both for the writedata(22 downto 20) addresses mentioned by Jozephka99 and those mentioned in the manual.
I've added my latest project as a zip file. In this latest test, I even just exported the csr interface and manually connected my signals to it.
I hope to find time this week to setup the signal tap so I can see what goes on in the actual FPGA and why this is failing. (or at least gives the impression of failing)
Already many thanks for the different people replying to this topic and helping me figuring this out!
Contributor"timeout" component file missing. So I cannot compile that project. Can you provide it?
