Honored Contributor
Honored ContributorI found the problem.
I started to think more about the Surce_valid output. The problem was that the output start after two cycles of FFT and "some delay": in my case the Souce_ready go up after 536 cycles of clock, 256+256+24. This delay creates issues in SIMULINK because the output buffer and so the vector scope start to display datas with a 24 clock delay: this is the cause of the spectrum shift displayed . I inserted a 232 delay before the output and so the ouput is syncronyzed with a FFT cycle delay. (But the purpose was to have an understandable right output so the issue is acceptable and my objective is accomplished). To avoid the one cycle delay I thought about insert a sort of trigger or switch in order to let flow the datas to the buffer only when the Source Valid goes on but I haven't find useful to me till now... Another thing to do is also to adjust the amplitude. Maybe there is an error inside the second power spectrum, I don't think i had to divide by 256 because the signal is not vectored before the buffer...but.. I post the new scheme and the new file, I hope it can be useful also to other people. PS: do you know if I need a new license to update my Quartus and my DSP builder from 7.2 to 8.1? http://img399.imageshack.us/img399/5143/schemaprogettorq5.jpg
