LVDS Serdes multi channel bit order (Cyclone 10 GX)

Hi designEngineer,

Serializer = Parallel data to Serial data, normally we call this as TX. Meaning parallel data from core become serial data at output pin.

Deserializer = Serial data to parallel and we call this as RX. Serial data to pin and pass thru the Deserializer block to parallel data to core.

For dual channel, SERDES factor of 8:

Let's assuming you have two channels as above and the pattern is repeated pattern for respective channel (rx_in & rx_in2). In which mean rx_in always 12345678 12345678 12345678…… and rx_in2 alaways abcdefgh abcdefgh abcdefgh...

When you create a design with dual channel in single IP, the representation block will be something as above and each parallel rx_out[15:0] are {12345678 abcdefgh} {12345678 abcdefgh} {12345678 abcdefgh} {12345678 abcdefgh}

I hope it is clear now.

Regards,

Matt