Forum Discussion

GiladA's avatar
GiladA
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Lvds load enable

I design LVDS SERDES IP of 700Mbps Data Rate with external PLL and Serdes factor of 8 on Stratix 10. In the lab i test the design with external loop and encounter a problem with the lsb in the RX (...
Transceiver
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    suggested PLL-parameters are displayed in parameter editor for SERDES IP. Expect -45° (-360/8) load_enable phase shift for 8 bit SERDES.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.